1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the chemical mechanical polishing of substrates having an uneven surface topology so as to remove excess material and to planarize the substrate surface, wherein two or more different material layers provided as a stack need to be polished.
2. Description of the Related Art
The fabrication of integrated circuits requires the deposition and subsequent patterning of material layers or stacks of material layers to form circuit elements, such as resistors, capacitors, transistors and the like. Since feature sizes of the circuit elements are steadily decreasing, whereas the diameter of the substrates on which the integrated circuits are manufactured has presently reached 300 mm, it is of great importance to precisely control the individual process steps in accordance with strictly-set process tolerances necessary for achieving a high production yield. For example, the photolithographic patterning of circuit elements strongly depends on the lithographic tool and the optical characteristics of the material layer to be patterned, including any overlying and underlying material layers. Therefore, the surface topography of the substrate, prior to the deposition of a photoresist, may have a significant influence on the patterning process. For this reason, it has become standard practice in the fabrication of sophisticated integrated circuits to planarize the substrate surface prior to critical process steps. One example in this respect is the formation of shallow trench isolation (STI) structures, which, in principle, are trenches formed in a substrate and filled with a dielectric material to electrically insulate adjacent substrate areas from each other. Since usually an extremely critical photolithography process for patterning gate electrodes of field effect transistors is carried out after formation of the STI structures, a thorough planarization of the substrate surface is required.
Since the chemical mechanical polishing (CMP) of substrates has been introduced for the first time in the fabrication of integrated circuits, this process technique has become a valuable and reliable means for providing a substantially planar substrate surface, even on large-diameter substrates. In chemically mechanically polishing a substrate, typically a chemical reagent is supplied to the surface of the substrate, usually in the form of a so-called slurry, which reacts with the material or materials to be removed. Simultaneously, the material and/or the reaction product thereof will be mechanically removed by abrasives that are present in a so-called polishing pad or that may also be supplied with the slurry. Upon establishing a relative motion between the substrate surface and the polishing pad, the material and/or the reaction product thereof is continuously removed, wherein the removal rate depends on the type of material, the type of slurry, i.e., the type of chemical reagent and the type of abrasives contained therein, the speed of the relative motion, the pressure with which the substrate is pressed on the polishing pad, the topography of the surface to be polished, and the like.
With reference to FIGS. 1 and 2, a typical process sequence for planarizing a substrate surface involving a CMP process will be discussed in more detail, thereby referring to a typical STI formation sequence. In FIG. 1a, a semiconductor structure 100 comprises a substrate 101, for example, a silicon substrate, having formed therein a plurality of trenches 102, and covered by a layer 103 of a dielectric material, such as silicon dioxide. Moreover, a silicon nitride layer 104 is provided outside the trenches 102 beneath the silicon dioxide layer 103. For convenience, any additional layers, such as a pad oxide layer underlying the silicon nitride layer 104 and an oxide layer within the trenches 102 that may be thermally grown, are not depicted in FIG. 1a. 
Typically, the silicon nitride layer 104 is patterned by a photolithography process and is etched first, and then the trenches 102 are formed in the substrate 101 by performing an anisotropic etch process. Subsequently, the silicon dioxide 103 is deposited after forming a thin thermally grown oxide in the trenches 102 by appropriate deposition methods, such as chemical vapor deposition, to reliably fill the trenches 102. It is, therefore, necessary to deposit oxide in excess on the substrate 101, thereby creating a surface topography depending on the underlying structure defined by the trenches 102. As previously explained, excess material of the layer 103 is removed by CMP, wherein the silicon nitride layer 104 acts as a so-called stop layer to significantly “slow down” the CMP process by reducing the total removal rate once the overlying silicon dioxide is removed. The oxide layer 103 is provided with a thickness Dox targeted to reliably fill the trenches, as indicated in FIG. 1a, whereas the silicon nitride layer 104 has an initial layer thickness indicated by DiNit that is sufficiently large to stop the CMP process after having reliably removed the excess oxide without damaging the underlying substrate 101.
FIG. 1b schematically shows the semiconductor structure 100 after completion of the CMP step, wherein the excess oxide 103 over active regions is completely removed, and wherein the silicon nitride layer 104 has been partially removed to form a final silicon nitride, layer indicated by 104a, having a thickness at the end of the CMP process indicated by DfNit. In this CMP process, it is extremely important to precisely control process parameters such that the final thickness of the silicon nitride layer 104a, DfNit matches a target value within strictly-set tolerances, since any overpolishing of the silicon nitride layer 104a may damage the underlying substrate 101, in which circuit elements, such as active areas of transistor elements, have to be formed. On the other hand, a silicon nitride layer 104 having a thickness DfNit exceeding the target value may have an adverse impact on the following critical photolithography patterning process, in which gate electrodes with dimensions of 0.25 μm and less may have to be formed.
Since it is extremely difficult, if not impractical, to measure the remaining thickness of the silicon nitride layer 104 at a predefined site of the substrate during the CMP process, it is attempted to “predict” the point in time when the targeted value for the thickness DfNit of the final silicon nitride layer 104a is reached. Since a plurality of different parameters have a significant influence on the CMP process, and since it is extremely difficult to individually control the plurality of process parameters, it is necessary to precisely monitor the removal rate, which represents the effect of the totality of the process parameters, so that, by selecting an appropriate process time, the final thickness of the silicon nitride layer 104a may be controlled. One possibility of monitoring the removal rate of the CMP is to determine the oxide thickness Dox and the final thickness DfNit of the silicon nitride layer 104a and the process time of a previously polished substrate to obtain an estimation of the actual removal rate. It turns out, however, that polishing a substrate on the basis of the previous removal rate may lead to a significant deviation of the final thickness DfNit from the target value, thereby jeopardizing the subsequent process steps, as is described earlier. This discrepancy between the target value and the actual thickness DfNit occurs for the following reasons. First, the removal rate may change during the actual CMP process so that, at the beginning of the instantaneous CMP process, a slightly different removal rate may prevail, especially when measurement results, on which the removal rate prediction is based, may be provided with a certain process-inherent delay. Second, at a certain stage of the CMP process, the removal rate is actually a composition of two terms that may per se exhibit quite different values. For instance, after removing the excess oxide of the layer 103, having a thickness of Dox, the substrate surface includes portions with oxide 103 and portions with silicon nitride 104 that are to be simultaneously removed. Due to the quite different material properties, the removal rate of oxide and silicon nitride are quite different, wherein any variation of the nitride layer 104, for example, a variation of the initial layer thickness DiNit, may have a significantly larger impact on the polish process than any variation of the oxide layer 103, so that the final thickness DfNit may not meet the process requirement.
FIG. 2 depicts, in a schematic manner, a typical progression of the removal rate during an STI polish process as depicted in FIGS. 1a and 1b during a first polish period, indicated as I, in which only the oxide 103 is removed. After planarizing the hills and valleys of the oxide layer 103, the initially high removal rate stabilizes at a substantially constant value indicated by RI. At the end of period I, the silicon nitride layer 104 is exposed, and, thereafter, large areas of silicon nitride and the oxide in the trenches 102 are polished simultaneously, wherein due to the reduced removal rate of silicon nitride, the total removal rate rapidly drops to a second substantially constant removal rate indicated as RII.
In order to obtain a desired final thickness DfNit of the nitride layer 104a, despite the above-identified difficulties, typically, the polish time for a substrate to be processed is calculated in a feed forward manner on the basis of the measured oxide thickness Dox, the target value for the final thickness of the silicon nitride layer 104a, in the following noted as DNittarget, and a model of the CMP process. These predictive CMP models are typically based on the initial oxide thickness Dox, however, slight variations of the initial thickness DiNit of the silicon nitride layer 104 or in the material composition may lead to a significant deviation from the target value DNittarget for the final silicon nitride layer 104a. Thus, although the conventional CMP process control based on the oxide layer thickness measurement allows a significant improvement in predicting an appropriate polish time, there is still room for improvement of the CMP control to especially take into account any variations of the initial silicon nitride layer 104.
In view of the problems identified above, it is desirable to provide a technique that allows the planarization of patterned layer stacks comprising two or more different materials.